About Me
I’m a student at Xidian University (2023.9 - Present), studying Digital IC Design.
Interests
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Computer Architecture: I’m passionate about understanding how computers work at a fundamental level.
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Formal Verification: I have a keen interest in ensuring the correctness of hardware designs through formal methods.
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AI Accelerators: I’m fascinated by the design and optimization of hardware for artificial intelligence applications.
Projects
Check out my GitHub for my work on Verilog modules and other projects.
Contact
Feel free to reach out via GitHub!
